FIELD OF THE INVENTION
The present invention relates to a circuit configuration for reducing disturbances caused by switching an output driver. The circuit configuration has individual output driver stages. A switching signal is supplied to the individual stages for switching the output driver on or off. The switching signal has a time delay between each of the individual stages, in order to switch the output driver stage by stage. Circuit configurations of this type are for instance described and shown in the German Published, Non-Prosecuted Patent Application DE 42 00 680 A1 or in the textbook "Digital MOS Integrated Circuits II," edited by Mohamed I. Elmasry, 1992, ISBN O-87942-275-0, on pages 385-92, and in particular in FIG. 5 on page 388.
Digital semiconductor components with a large number of outputs, such as 16 or more outputs, have a considerable disturbance in the supply voltage when the output driver stages at the respective outputs are switched simultaneously. This phenomenon is generally known, inter alia, as "dI/dt noise", "groundbounce", "simultaneous switching noise", etc. Switching large currents on or off results in an increased disturbance.
When a plurality of output driver stages are switched simultaneously, the disturbance acting on the supply voltage increases with an increasing supply voltage, since switching large output currents requires a high supply voltage.
In order to reduce supply voltage disturbances caused by simultaneous switching, it has been suggested to provide a circuit arrangement with output driver stages connected in parallel, wherein the output driver stages are switched in a time delayed manner rather than being switched simultaneously. The current changes caused by the parasitic inductances of the digital semiconductor components are reduced by this temporally delayed or staggered switching of the individual output driver stages connected in parallel with one another.
FIG. 3 shows such a circuit configuration with output driver stages 1, 2, which are driven via an input terminal 3 and which are connected in parallel to an output terminal 4. The output driver stages 1, 2 are driven such that at first the output driver stage 1 is driven and then, with a delay, the output driver stage 2. The delay is effected by a delay element 5. The delay element 5 operates such that the resulting time delay decreases with an increasing supply voltage VCC.
Switching the individual output drivers time-delayed with respect to one another is advantageous in reducing the above-mentioned disturbances of the supply voltage. However, this advantage is at the expense of the total signal delay of such a circuit configuration which increases as a result of the time delayed switching on of the individual output driver stages. This undesirable effect is most prominent when the time delay between switching on the individual output driver stages is longest, that is to say when the supply voltage is low. This is due to the fact that in the conventional circuit configurations, which use common output drivers, the signal delay increases with a decreasing supply voltage. In other words, the higher the supply voltage the shorter the time delay between the individual output driver stages. This means that the disturbance reduction is smallest at a high supply voltage, just when most of the disturbances occur. This is the reason why conventional circuit configurations for reducing disturbances caused by switching an output driver operate inadequately, in particular with high supply voltages when the reduction of disturbances is reduced by the diminishing time delay between the output driver stages.